Digital
Follow the logic.
Upload a supported Verilog design and testbench, then inspect the simulation logs and VCD waveform.
The platform
Upload your design.
Run it. Explore the results.
Start with your own files or a sample design. Run a simulation, then inspect the available waveforms and logs to see how your circuit behaves.
Circuit explorer
From the source.To the signal.
To the insight.
01 / Digital counterIllustrative · not a live run
Switch between digital and analog.Browser workspace
Analog
See the response.
Run a supported SPICE netlist with ngspice and review available CSV waveform output.
Connected work
The result is part
of the project.
Projects
Group related designs and simulation runs. Keep digital and analog work organized.
Results
Find logs and available waveforms. Revisit stored outputs within your workspace retention period.
Workspace
Invite teammates with workspace roles. Keep your usage and plan limits visible.
A completed run means the simulator exited normally. Review your testbench assertions and outputs to validate the design’s behavior.
AI result explanations · planned for launch
Understand what
the result is telling you.
Request an explanation of selected logs and result summaries. Review warnings and suggested next steps alongside the original simulator output.
Explore launch plans ›You stay in control.
AI explanations are not enabled yet. At launch, you choose when to share supported result data, review provider information, and see your remaining allowance.
An explanation supports your review; it does not certify that the design is correct.
Explore it with your team.
Start with a sample or arrange a walkthrough.